1 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver fast cmos address/clock driver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t logic block diagram product description pericom semiconductors pi74fct series of logic circuits are produced in the companys advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct162344t is an address/clock driver designed to provide the ability to fanout to memory arrays. eight banks, each with a fanout of four, and 3-state control, provide efficient address distribution. one or more banks may be used for clock distribution. the pi74fct162344t has balanced output drivers. it is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this eliminates the need for external terminating resistors for most interface applications. product features ? ideal for address line driving and clock distribution ? eight banks with 1:4 fanout with 3-state control ? typical t sk ( o ) output skew < 500ps ? balanced output drivers: 24ma ? hysteresis on all inputs ? packages available: C 56-pin 240-mil wide plastic tssop (a) C 56-pin 300-mil wide plastic ssop (v) a 1 b 11 oe 1 b 14 a 2 b 21 b 24 a 5 b 51 oe 3 b 54 a 6 b 61 b 64 a 3 b 31 oe 2 b 34 a 4 b 41 b 44 a 7 b 71 oe 4 b 74 a 8 b 81 b 84
2 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver product pin configuration 56-pin a56 v56 product pin description pin name description oe x 3-state output enable inputs (active low) ax inputs bxx 3-state outputs gnd ground v cc power inputs outputs oe x a x bxx lll lhh hxz truth table (1) capacitance (t a = 25c, f = 1 mhz) parameters (1) description test conditions typ max. units c in input capacitance v in = 0v 3.5 6.0 pf c out output capacitance v out = 0v 3.5 8.0 pf note: 1. this parameter is determined by device characterization but is not production tested. note: 1. h = high voltage level l = low voltage level x = dont care z = high impedance 1 2 3 4 5 6 7 v cc 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 b 11 oe 1 b 12 gnd b 13 b 14 a 1 b 21 b 22 gnd b 23 b 24 b 31 a 2 a 3 b 32 gnd b 33 b 34 v cc b 41 b 42 gnd b 43 b 44 oe 2 a 4 v cc b 81 oe 4 b 82 gnd b 83 b 84 a 8 b 71 b 72 gnd b 73 b 74 b 61 a 7 a 6 b 62 gnd b 63 b 64 v cc b 51 b 52 gnd b 53 b 54 oe 3 a 5
3 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ......................................................... C65c to +150c ambient temperature with power applied ....................... 0c to +70c supply voltage to ground potential ................................. C0.5v to +7.0v dc input voltage .............................................................. C0.5v to +7.0v dc output current ............................................................ C60 to +120 ma power dissipation .............................................................. 0.5w dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min, v in = v ih or v il i oh = C 24ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24ma 0.3 0.55 v v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v cc = max. v in = v cc (input pins) 1 a i il input low current v cc = max. v in = gnd (input & i/o pins) 1 a i ozh high impedance v cc = max. v out = 2.7v 1 a i ozl output current (3-state output pins) v out = 0.5v 1 v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v i odh output high current v cc = 5v, v in =v ih or v il , v out = 1.5v (3) C60 C115 C150 ma i odl output low current v cc = 5v, v in =v ih or v il , v out = 1.5v (3) 60 115 150 ma i os short circuit current (4) v cc = max., v out = gnd (4) C80 C140 C225 ma i out output drive current v cc = max., v out = 2.5v (3) C50 C180 ma v h input hysteresis 100 mv operating range ambient temperature = C40c to +85c vcc = 5.0v 10% note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. this parameter is determined by device characterization but is not production tested. 4. not more than one output should be shorted at one time. duration of the test should not exceed one second.
4 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 500 a supply current d i cc supply current per v cc = max. v in = 3.4 v (3) 0.5 1.5 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 170 220 a/ input per mhz (4) outputs open v in = gnd mhz oe x = gnd one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 1.7 2.7 (5) ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle oe x = gnd one bit toggling v in = 3.4 v 2.0 3.5 (5) v in = gnd v cc = max., v in = v cc 3.4 4.9 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle oe x = gnd 16 bits toggling v in = 3.4 v 5.4 10.9 (5) v in = gnd notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0 v, +25c ambient. 3. per ttl driven input (v in = 3.4 v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + fini) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4 v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) fi = input frequency ni = number of inputs at fi all currents are in milliamps and all frequencies are in megahertz.
5 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver 162344at 162344ct 162344et com. com. com. parameters description conditions (1) min max min max min max unit t plh propagation delay c l = 50pf 1.5 4.8 1.5 4.3 1.5 3.8 ns t phl a x to b x r l = 500 w t pzh output enable time 1.5 6.2 1.5 5.8 1.5 5.0 ns t pzl oe x to b x t phz output disable time 1.5 5.6 1.5 5.2 1.5 4.6 ns t plz oe x to b x t sk 1 (o) (3,5) output skew 0.5 0.35 0.25 ns t sk 2 (o) (4,5) output skew 0.5 0.5 0.3 ns switching characteristics over operating range notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between outputs of the same bank and same package, switching in the same transition. 4. skew between outputs of all banks of the same package with a1 through a8 tied together, switching in the same transition. 5. this parameter is guaranteed but not production tested. tests circuits for all outputs (1) test switch disable low 7v enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. pulse generator d.u.t. v in r t v out c l 500 w 500 w 50pf v cc 7.0v
6 ps2047b 03/22/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162344t address/clock driver switching waveforms output skew C t sk 1 (o), t sk 2 (o) propagation delay enable and disable times note: t sk 1 (o) = ox and oy are in the same bank. t sk 2 1 (o) = ox and oy are in a different bank on the same port. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com input t plh 3v 1.5v 0v output v oh 1.5v v ol t phl t pzl oe 1.5v 0v 3v 1.5v 3.5v 0v 1.5v t plz v ol 3.5v 0v t pzh t phz 0.3v 0.3v output normally low output normally high switch closed switch open v oh enable disable input t plhx 3v 1.5v 0v ox v oh 1.5v v ol t phlx t sk(o) oy v oh 1.5v v ol t sk(o) t plhy t phly t sk(o) = | t plhy C t plhx | or | t phly C t phlx |
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